Transfer Function — Control Systems/Continues
Control_Systems/Continues/Transfer_Function · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Transfer Function
Control Systems / Continues
A continuous-time SISO transfer function in the Laplace variable:
H(s) = N(s) / D(s)
where the coefficient vectors are given in descending powers of s, so [2 1] over [1 2 1] is (2s + 1) / (s2 + 2s + 1).
Ports
- Input – the signal to filter, of any size [p,m].
- Output – the filtered signal, of the same size.
The function is SISO, but it is applied independently to every entry of the input signal, each entry carrying its own states.
Parameters
- Numerator – N(s) coefficients, highest power first.
- Denominator – D(s) coefficients, highest power first. It must be at least the numerator's order, and its leading coefficient must be non-zero.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one emits the direct-form difference equation of the discretized function – the same recursion the discrete run realizes – so generated code matches the in-app simulation.
Simulink bridge
Import and export, mapped to simulink/Continuous/Transfer Fcn.
"Numerator" to Numerator, "Denominator" to
Denominator, "Sampling Time (s)" to SampleTime.
Nothing is left behind – every parameter has a counterpart.
Notes
- Stateful: as many states per input entry as the denominator's order.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Continues/Transfer_Function |
| family | Control_Systems/Continues |
| solver environment class | ICoreBlock_0_Control_Systems_1_Continues_2_Transfer_Function |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Transfer_Function/ICoreBlock_0_Control_Systems_1_Continues_2_Transfer_Function.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Continues/Transfer_Function/ICoreBlock_0_Control_Systems_1_Continues_2_Transfer_Function.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator | [2 1] | Numerator |
Denominator | [1 2 1] | Denominator |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Continuous/Transfer Fcn |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Numerator | Numerator | passes through |
Denominator | Denominator | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Transfer Function block — element-wise (non-scalar) handling The block defines ONE SISO transfer function (num/den), but the input port may carry a [p,m] matrix signal. The same transfer function is applied INDEPENDENTLY to each of the K = p*m entries, and the output is a [p,m] matrix of the per-entry results. There is no cross-coupling between entries — entry e of the input maps only to entry e of the output.
Simulation (compute_f / compute_h, continuous & discrete) The SISO realization has n states. Rather than loop, we vectorize across entries:
- Block state X is [n, K] — column e holds the n-state vector of entry e.
- Input U is [1, K] — the [p,m] input flattened to a single row (tfFlattenToRow).
The plain state-space products then evaluate every entry at once, since B/D are SISO: A*X + B*U -> [n,K] (column e = A*x_e + B*u_e) (state evolution) C*X + D*U -> [1,K] (column e = C*x_e + D*u_e) (output) The [1,K] output row is reshaped back to the input's [p,m] (tfReshapeLike). Flatten and reshape both go through rawData(), so the entry<->entry mapping is purely positional.
State sizing: X must be [n, K]. setInitialState([n,K]) is done in BOTH initializePortSignalSize AND at the end of loadBlockConfig, because initializeStateSpace_Continues() resets the state to [n,1]; loadBlockConfig runs last (at simulation start), so it must re-establish [n,K] — otherwise only scalar [1,1] inputs would solve.
Code export (Python/MATLAB/Java/Rust/C/C++ and HDL/PLC) Every generator realizes the SAME discretized direct-form IIR difference equation, but with per-entry history buffers, looping over the output port's [p,m] dimensions so each entry gets its own independent u/y history. See the per-language sections below.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.004975 … 0.1722 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.782 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.851 … 0.8685 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.6479 … 0.8972 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Continues__Transfer_Function.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).