Unary Minus — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Unary_Minus · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Unary Minus
Control Systems / Base Blocks
Negates its input, entry by entry: y = −u. The block has no parameters – what it computes is fixed – and is the compact way to flip a signal's sign without spending a Gain of −1 on it.
Ports
- Input – the signal u, of any size [m,n].
- Output – the negated signal y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to expose as a tunable parameter: the negation is the block, so it is emitted straight into the arithmetic.
The three HDL targets are fully synthesizable. Negating a Q16.16 value is a two's complement negate – no shift, no divider, no function call – so unlike the square-root family the generated cores carry the block's own arithmetic rather than a simulation-only stand-in.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Unary Minus.
The block has no configuration to translate, so the only pair is the global one:
"Sampling Time (s)" to SampleTime, as on every block. Simulink's
SaturateOnIntegerOverflow has no counterpart – it governs
integer and fixed-point data types, and ICore signals are doubles.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Linear, so the block carries a feed-through continuous state space with D = −I. That is what lets model reduction absorb it into a neighbouring plant; a negation that carried none would refuse a merge that is otherwise trivially valid.
- To scale as well as negate, use Gain; to subtract two signals, use Subtract.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Unary_Minus |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Unary_Minus |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Unary_Minus/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Unary_Minus.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Unary_Minus/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Unary_Minus.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Unary Minus |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Unary Minus block -- negate a signal y = -u, entry by entry. Algebraic, stateless, and the same size in as out.
It carries a FEED-THROUGH STATE SPACE (D = -I). That is not decoration: a block without one is refused by the series/parallel/feedback reduction commands, so a negation sitting between two plants would block a merge that is otherwise trivially valid -- and -I is exactly the matrix the merge needs. The same call Gain makes for its own gain matrix, minus the modes.
Nothing here is fixed point-hostile: negating a Q16.16 value is a two's complement negate, so all three HDL targets are fully synthesizable, unlike the Sqrt family next door.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 2 |
| 0.4 | 0.5 | -0.5 |
| 0.8 | -2 | 2 |
| 1.2 | 0.5 | -0.5 |
| 1.6 | -2 | 2 |
| 2 | 0.5 | -0.5 |
| 2.4 | -2 | 2 |
| 2.8 | 0.5 | -0.5 |
| 3.2 | -2 | 2 |
| 3.6 | 0.5 | -0.5 |
| 4 | -2 | 2 |
| 4.4 | 0.5 | -0.5 |
| 4.8 | -2 | 2 |
| 5.2 | 0.5 | -0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -1 … 0 |
ramp | Ramp: slope 1 from t = 0 | -5.8 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.9996 … 1 |
step | Step: 0 -> 1 at t = 1 s | -1 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Unary_Minus.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).