Squeeze — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Squeeze · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Squeeze
Control Systems / Base Blocks
Removes singleton dimensions from a multidimensional signal, exactly as
MATLAB's squeeze does – a 3×1×2 signal becomes
3×2. The block has no parameters.
On an ICore signal it is a pass-through, and always will be. An ICore
signal is a two-dimensional matrix [m,n] and nothing else, and
squeeze is defined to act only where there are more than two
dimensions – so there is never a singleton dimension for it to drop, and
y = u unchanged, including for a [1,n] row or an [m,1] column. That is
what the operation MEANS on a two-dimensional signal, not a limitation of this
implementation; Simulink's own Squeeze passes a 1×1 and a 3×1
through untouched too.
The block exists so that a Simulink model containing one imports and exports whole. To change a signal's shape, use Reshape, which does exactly that and is the block most people arriving here are looking for.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, the same values in the SAME size [m,n].
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each emits a copy from the input signal to the output signal – there is no arithmetic to get wrong, and nothing to expose as a tunable parameter. The three HDL targets are fully synthesizable: the copy is a wire.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Squeeze.
Nothing crosses but the block itself: the Simulink block defines
no dialog parameters at all, not even SampleTime, so the
entry sets hasSampleTimeParam = false and "Sampling Time (s)" stays
on the ICore side. Writing that parameter anyway would be a hard
set_param error in MATLAB rather than a warning, aborting the whole
generated script.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Linear – it is the identity – so the block carries a feed-through continuous state space with D = I and model reduction merges straight through it. A pass-through that refused to merge would be an obstacle invented out of nothing.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Squeeze |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Squeeze |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Squeeze/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Squeeze.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Squeeze/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Squeeze.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Squeeze |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: Simulink's Squeeze block defines no dialog parameters at all, so "Sampling Time (s)" stays on the ICore side
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Squeeze block -- drop singleton dimensions Simulink's Squeeze removes dimensions of size one from a MULTIDIMENSIONAL signal: a 3x1x2 becomes 3x2. It is MATLAB's squeeze(), and MATLAB's squeeze() of a two-dimensional array is the identity -- squeeze only ever acts where ndims > 2.
AN ICORE SIGNAL IS AN ICoreMatrix, i.e. always exactly two-dimensional. So on every signal this block can ever be handed, squeeze IS the identity, and this block is a pass-through. That is not an approximation or an unfinished implementation; it is what the operation means on the signals ICore carries, and it was confirmed against the real block rather than assumed: Simulink's Squeeze fed a 1x1 and a 3x1 passes both through unchanged.
SO WHY HAVE IT. Because a Simulink model that contains one has to survive the round trip. Without this block the bridge reports the type as unmapped and drops it, breaking the links either side; with it, the diagram imports whole, runs, and exports back to the same Simulink block. The block's own description says plainly that it is a pass-through here, so nobody reaches for it expecting a reshape -- Reshape is next door and does that.
It is LINEAR, so it carries a feed-through state space with D = I. A pass-through that refused model reduction would be an obstacle invented out of nothing.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Squeeze.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).