Sqrt — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Sqrt · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Sqrt
Control Systems / Base Blocks
Takes a square root of the input, entry by entry, in one of three forms chosen by the Operator parameter: the plain root y = √u, the signed root y = sign(u)·√|u| which extends it to negative inputs, or the reciprocal root y = 1/√u.
Ports
- Input – the signal u, of any size [m,n]. Which values are in domain depends on the operator, and is listed with each option below.
- Output – the rooted signal y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Operator – which root is taken. This selects the arithmetic
rather than retuning it, so each option is a separate code path.
- Square Root (sqrt(u)) – y = √u. Defined for u ≥ 0; a negative entry is out of domain and yields NaN. This is the default, as in Simulink.
- Signed Square Root (sign(u)*sqrt(|u|)) – the root of the magnitude, carrying the input's sign. Defined for every real input, and the only option with no out-of-domain values.
- Reciprocal Square Root (1/sqrt(u)) – y = 1/√u. Defined for u > 0; zero yields +Inf and a negative entry yields NaN.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The operator is fixed into the generated arithmetic at export time rather than exposed as a tunable parameter: it selects which code is emitted, so there is nothing left to retune on the generated core.
The seven software targets agree exactly, including out of domain, where they
all produce IEEE NaN or +Inf. MATLAB needs one extra step to get there: its
sqrt of a negative real returns a complex number rather than
NaN, so the generated MATLAB maps negative entries to NaN first and keeps the
result real.
The three HDL targets are simulation-only. There is no square root in
the Q16.16 datapath to call, so the generated cores convert at the port boundary
and evaluate the root in real arithmetic – correct in
simulation, but not offered as synthesizable. They also carry neither NaN nor
infinity, so out of domain they answer 0 where the software targets
answer NaN or +Inf. Keep the input inside the operator's domain if the exported
core has to agree with the reference everywhere.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Sqrt.
"Operator" to Operator, one option for one option
(sqrt, signedSqrt, rSqrt), so that round
trip is lossless; "Sampling Time (s)" to SampleTime, as on every
block.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear in any of the three operators, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Simulink's Signed Sqrt and Reciprocal Sqrt library entries are this same block pre-set to those operators, and import as such.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Sqrt |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sqrt |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sqrt/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sqrt.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sqrt/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sqrt.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Operator | Square Root (sqrt(u))%~%Signed Square Root (sign(u)*sqrt(… | Operator |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Sqrt |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Operator | Operator | Square Root (sqrt(u)) → sqrt, Signed Square Root (sign(u)*sqrt(|u|)) → signedSqrt, Reciprocal Square Root (1/sqrt(u)) → rSqrt |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Sqrt block -- square root, in Simulink's three flavours Operator selects WHICH code runs, so it is a mode, not a tuning: Square Root y = sqrt(u) Signed Square Root y = sign(u) * sqrt(|u|) Reciprocal Square Root y = 1 / sqrt(u) Entry by entry. Algebraic and stateless, no state space (see header).
Two conventions are worth stating because they are the only places the ten targets could have drifted:
- OUT OF DOMAIN. sqrt of a negative and rSqrt of zero have no real answer. The seven
software targets all produce IEEE NaN / +Inf and agree exactly -- except MATLAB, whose sqrt() of a negative real returns a COMPLEX number rather than NaN, so the MATLAB body maps the negative entries to NaN first and keeps the result real, matching the other six.
- HDL. Q16.16 fixed point carries neither NaN nor infinity, so the three HDL backends
answer 0 there instead. They are also SIMULATION-ONLY: there is no fixed-point square root to call, so they convert at the port boundary and evaluate in
real.
Sample results#
25 sample(s) were non-finite (nan/inf) and are absent from the plot; they are in the table below and in the JSON.
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | nan |
| 0.4 | 0.5 | 0.7071 |
| 0.8 | -2 | nan |
| 1.2 | 0.5 | 0.7071 |
| 1.6 | -2 | nan |
| 2 | 0.5 | 0.7071 |
| 2.4 | -2 | nan |
| 2.8 | 0.5 | 0.7071 |
| 3.2 | -2 | nan |
| 3.6 | 0.5 | 0.7071 |
| 4 | -2 | nan |
| 4.4 | 0.5 | 0.7071 |
| 4.8 | -2 | nan |
| 5.2 | 0.5 | 0.7071 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 2.408 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0.9998 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Sqrt.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).