Sign — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Sign · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Sign
Control Systems / Base Blocks
Outputs the sign of its input and nothing else: y = −1 where u is negative, y = 0 where u is exactly zero, and y = +1 where u is positive. Applied entry by entry, so a matrix signal is tested element for element.
Ports
- Input – the signal u, of any size [m,n].
- Output – the signum y, of the SAME size [m,n], every entry one of −1, 0 or +1. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core.
Only Python and MATLAB use a built-in; the other eight emit the three-way
test explicitly. That is deliberate and is about the zero case: Rust's
f64::signum answers +1 for 0.0, and C, C++ and the three HDL
targets have no signum to call at all. Writing the test out is what makes all
ten agree on the one input where a built-in would not.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Sign. The block
has no parameters of its own, so the only pair is the global one:
"Sampling Time (s)" to SampleTime, as on every block. Simulink's
zero-crossing detection is a solver setting rather than a block behaviour and
does not cross.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, and the discontinuity at the origin IS the block, so it deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing the step.
- The zero output is a genuine third level, not a rounding of one of the others. A signal that only ever approaches zero without reaching it never produces it, which is why a random test stimulus exercises two of the three branches and the third has to be driven deliberately.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Sign |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sign |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sign/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sign.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Sign/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Sign.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Sign |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Sign block -- signum y = -1 / 0 / +1 as u is negative / zero / positive, entry by entry. Algebraic and stateless, no state space (see header).
The zero case is where the targets' built-ins part company, so most of them do NOT get their built-in here: Rust's f64::signum returns +1.0 for 0.0 (and -1.0 for -0.0), and C and C++ have no signum at all. Every target therefore emits the same explicit three-way test, which is also what keeps the three HDL backends -- which have nothing to call -- bit-identical to the reference.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -1 |
| 0.4 | 0.5 | 1 |
| 0.8 | -2 | -1 |
| 1.2 | 0.5 | 1 |
| 1.6 | -2 | -1 |
| 2 | 0.5 | 1 |
| 2.4 | -2 | -1 |
| 2.8 | 0.5 | 1 |
| 3.2 | -2 | -1 |
| 3.6 | 0.5 | 1 |
| 4 | -2 | -1 |
| 4.4 | 0.5 | 1 |
| 4.8 | -2 | -1 |
| 5.2 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Sign.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).