Second Order Integrator — Control Systems/Base Blocks

Second-Order Integrator

Control Systems / Base Blocks

Integrates its input twice with respect to time: d²x/dt² = u, the transfer function 1/s². It reports both the position x and the velocity dx/dt. The integrator is scalar and is applied independently to every entry of the input signal, so both outputs have the input's size.

Ports

• Input u – the second derivative to integrate, of any size [m,n].
• Output x – the twice-integrated signal, of the same size.
• Output dx/dt – the once-integrated signal (the velocity), of the same size.

Parameters

• Initial Value x / Initial Value dx/dt – the two states at the start of the run. A scalar is broadcast to every entry; a matrix must match the input's size exactly.
• Limit x – off or on. When on, x is held inside Upper Limit x / Lower Limit x and integration of x stops at a limit instead of winding up.
• Upper Limit x / Lower Limit x – the band for x, used only while Limit x is on. They default to the widest finite doubles, which stand in for Simulink's ±infinity.
• Limit dx/dt – off or on. When on, dx/dt is held inside its own band and stops integrating at a limit, exactly as x does.
• Upper Limit dx/dt / Lower Limit dx/dt – the band for dx/dt, used only while Limit dx/dt is on.
• Wrap x – off or on. When on, x is wrapped into Wrapped Lower Value x … Wrapped Upper Value x instead of growing without bound – the usual choice for an angle. Wrapping and Limit x are alternatives: with both on, wrapping is applied and the block reports that the x band was ignored.
• Wrapped Upper Value x / Wrapped Lower Value x – the wrap range, used only while Wrap x is on. They default to ±π.
• Reinitialize dx/dt at Saturation – off or on. When on, reaching either x limit also forces dx/dt to zero, so the velocity does not survive an impact. Meaningful only while Limit x is on.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The exported block carries the discretization of the scalar 1/s² system for the run's method, so generated code matches the in-app simulation for every method, not just forward Euler. The twelve recursion coefficients are baked into the body at export time; the limits, the wrap range and the initial states are baked in too, so none of them is retunable on the generated core.

Wrapping costs a floored modulo. On the three HDL targets that is evaluated in Q16.16 through a constant reciprocal, so a wrap range that is not a clean binary fraction carries up to one quantum (about 1.5×10^-5) of extra error per wrap; the software targets use their native floor and do not.

Wrapping and reinitialization are verified on the seven software targets only. Both put a discontinuity – a wrap boundary, a saturation latch – under the control of a state that has been integrated twice. The HDL datapath carries that state in Q16.16, integration turns the quantum into a slow drift, and the drift moves the step at which the state crosses the trigger. The exported core is correct either side of that step, but a sample-by-sample comparison against a double-precision reference scores the whole jump whenever the two disagree about which sample it falls on, so the suite reports those combinations as not comparable rather than passing or failing them. The HDL cores themselves are unaffected: with limiting alone, or with neither, all three targets are verified normally.

Simulink bridge

Import and export, mapped to simulink/Continuous/Integrator, Second-Order. "Initial Value x" to ICX, "Initial Value dx/dt" to ICDXDT, "Limit x" to LimitX, "Upper/Lower Limit x" to UpperLimitX/LowerLimitX, "Limit dx/dt" to LimitDXDT, "Upper/Lower Limit dx/dt" to UpperLimitDXDT/LowerLimitDXDT, "Wrap x" to WrapX, "Wrapped Upper/Lower Value x" to WrappedUpperValueX/WrappedLowerValueX, and "Reinitialize dx/dt at Saturation" to ReinitDXDTwhenXreachesSaturation.

Simulink's Integrator, Second-Order Limited is the same Simulink block with its limits preset on, so it imports to this block too, with those presets applied. The block always shows both outputs from internal initial conditions (ShowOutput both, ICSourceX and ICSourceDXDT internal). External reset does not cross, nor do external initial conditions: both show extra input ports in Simulink, and no config value here can add or remove a port. This Simulink block has no SampleTime parameter, so "Sampling Time (s)" stays on the ICore side and an explicitly rated block reports that its rate did not cross.

Notes

• Stateful: two continuous states per input entry, x and dx/dt.
• Wrapping is applied to the x output rather than to the stored state. Neither dx/dt = v nor dv/dt = u depends on x, so the trajectories are identical, and the continuous and discrete paths stay in exact agreement.