Rounding Function — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Rounding_Function · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Rounding Function
Control Systems / Base Blocks
Rounds its input to a whole number, entry by entry, by one of four rules chosen with the Operator parameter: y = floor(u), ceil(u), round(u) or fix(u). All four are defined for every real input and none of them changes the signal's size.
Ports
- Input – the signal u to be rounded, of any size [m,n].
- Output – the rounded signal y, the SAME size [m,n] as the input. Every entry is a whole number, but it is still carried as a real signal, not an integer type.
Parameters
- Operator – which rounding rule is applied. This selects the
arithmetic rather than retuning it, so each option is a separate code path.
- Floor (toward -Inf) – the largest whole number not greater than u. floor(2.7) = 2, floor(−2.1) = −3. This is the default, as in Simulink.
- Ceiling (toward +Inf) – the smallest whole number not less than u. ceil(2.1) = 3, ceil(−2.7) = −2.
- Round (nearest, ties away from zero) – the nearest whole number, and where u falls exactly halfway the one FURTHER FROM ZERO. round(0.5) = 1, round(−0.5) = −1, round(2.5) = 3. This is MATLAB's and Simulink's convention; it is not banker's rounding, which would give 0, 0 and 2.
- Fix (toward zero) – the whole part, discarding the fraction. fix(2.7) = 2, fix(−2.7) = −2. Equal to Floor for a positive input and to Ceiling for a negative one.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The operator is fixed into the generated arithmetic at export time rather than exposed as a tunable parameter: it selects which code is emitted, so there is nothing left to retune on the generated core.
The seven software targets agree exactly, including on ties. Three of them
need more than the obvious call to get there, and the generated code says so:
Python's np.round is banker's rounding and Java's
Math.round breaks ties toward +Inf, so both build
Round from a truncation instead; IEC Structured Text has no rounding
function at all and builds all four from TRUNC.
The three HDL targets are synthesizable – unusually for this
family. Rounding a Q16.16 word is pure bit manipulation (an arithmetic shift
right by the fraction width is exactly a floor, negatives included), so nothing
is evaluated in real and the cores stay in the fixed-point
datapath. One caveat follows from that datapath rather than from the block: an
HDL input arrives already quantized to one part in
1.5×10⁻⁵, so an entry sitting within one quantum of a
.5 boundary can land on the far side of the tie and differ from the
software targets by a whole unit at that sample.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Rounding
Function. "Operator" to Operator, one option for one option
(floor, ceil, round, fix),
so that round trip is lossless; "Sampling Time (s)" to SampleTime,
as on every block. Those two are the only parameters the Simulink block
defines, so nothing is dropped in either direction.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear – all four operators are piecewise-constant step functions, and not differentiable at the steps – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Fix and Floor agree on every non-negative input, and Fix and Ceiling on every non-positive one. A test signal that never changes sign cannot tell those pairs apart.
- Simulink's Quantizer rounds to a LATTICE rather than to whole numbers, and is ICore's Quantizer; this block is the whole-number case.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Rounding_Function |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Rounding_Function |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Rounding_Function/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Rounding_Function.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Rounding_Function/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Rounding_Function.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Operator | Floor (toward -Inf)%~%Ceiling (toward +Inf)%~%Round (near… | Operator |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Rounding Function |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Operator | Operator | Floor (toward -Inf) → floor, Ceiling (toward +Inf) → ceil, Round (nearest, ties away from zero) → round, Fix (toward zero) → fix |
Caveat (shown to the user): the four operators map 1:1 onto Simulink's Operator values, so the choice is lossless in both directions; Operator and SampleTime are the only parameters the Simulink block defines, so nothing is dropped in either direction
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Rounding Function -- Simulink's four-operator Rounding Function, entry by entry "Operator" selects WHICH code runs, so every option is a mode rather than a tuning. All four are unary and TOTAL -- defined for every real input, no conditioning helper needed anywhere -- and none of them changes the block's shape.
TIES AWAY FROM ZERO is the whole difficulty, and it is a per-LANGUAGE trap. Measured against R2026a rather than assumed:
round([0.5 1.5 2.5 -0.5 -1.5 -2.5]) = [1 2 3 -1 -2 -3] (MATLAB, and this block)
Three of the ten targets get something else from the obvious spelling, and each would agree with the reference on almost every sample and diverge only on an exact half -- the failure that looks like noise rather than like a bug:
numpy np.round is BANKER'S rounding (ties to even). np.round(2.5) is 2, np.round(0.5) is 0. Built here from trunc(a + copysign(0.5, a)) instead. Java Math.round is ties-toward-+Inf AND returns a long. Math.round(-0.5) is 0 where MATLAB gives -1. Built here from copySign(floor(abs(a) + 0.5), a). PLC ST IEC 61131-3 has no rounding function at all -- only TRUNC, toward zero. Built from TRUNC(a +/- 0.5), the same idiom Quantizer uses.
C's round(), C++'s std::round and Rust's f64::round ARE ties-away-from-zero and are called directly. MATLAB's round() is the reference itself.
Note the half that is NOT a tie: 0.49999999999999994 is the double just below 0.5, and a + 0.5 rounds up to exactly 1.0 in IEEE. trunc() of that is 0, which is what MATLAB answers, so the trunc-based spellings agree there too -- but a floor(a + 0.5) spelling would answer 1 and be wrong. That is why the negative branch reflects rather than adding a signed half to a value that could carry it across an integer.
HDL: FULLY SYNTHESIZABLE, and the only block in this family that is. Rounding a Q16.16 word is pure bit manipulation -- an arithmetic shift right by the fraction width IS floor, for negatives included -- so there is no dynamic-range argument and nothing to evaluate in
real. The three HDL cores stay in the fixed-point datapath throughout. Their one real difference from the software targets is that a Q16.16 input is ALREADY quantized to 1.5e-5, so a sample sitting within one quantum of a .5 boundary can land on the far side of a tie; see the block's description, and the rig's config note.Algebraic and stateless. No state space -- see the header.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Rounding_Function.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).