Permute Dimensions — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Permute_Dimensions · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Permute Dimensions
Control Systems / Base Blocks
Reorders the input's dimensions according to Order. ICore signals are always two-dimensional, so there are exactly two orders: [2 1], which swaps them – the transpose, turning a [m,n] into an [n,m] – and [1 2], which leaves the signal alone.
Ports
- Input – the signal u, of any size [m,n].
- Output – [n,m] under the order [2 1], and [m,n] unchanged under [1 2]. This is one of the few blocks whose output dimensions differ from its input's.
Parameters
- Order – the new order of the dimensions, as a two-element
vector. It must be a permutation of 1 and 2:
- [2 1] – the dimensions swap. This is the transpose, and it is the default, as in Simulink.
- [1 2] – the identity. Accepted, and does nothing, so that a Simulink model using it crosses without being rejected.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The permutation is resolved at export time and the copy is unrolled, so no order branch survives into the generated core.
The three HDL targets are fully synthesizable. A permutation is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary or approximated.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Permute
Dimensions. "Order" to Order, passed through as the vector it
is.
The Simulink block has no SampleTime parameter, so the
rate is not carried across: it stays on the ICore side, and a block
configured with an explicit positive rate reports that the rate did not
cross.
Notes
- Algebraic, with no state – pure signal reindexing; nothing is scaled.
- Deliberately carries no state space, even though the transpose is linear: it reshapes, and a D matrix can rescale a signal but never re-index one.
- The order [2 1] computes what Math Function's Transpose operator computes. They are separate blocks in Simulink and separate here.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Permute_Dimensions |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Permute_Dimensions |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Permute_Dimensions/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Permute_Dimensions.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Permute_Dimensions/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Permute_Dimensions.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Order | [2 1] | Order |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Permute Dimensions |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Order | Order | passes through |
Caveat (shown to the user): ICore signals are always two-dimensional, so the only orders that mean anything here are [2 1] and [1 2]; Simulink's longer orders belong to signals of three dimensions or more and are reported rather than silently truncated
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Permute Dimensions -- the signal's dimensions reordered ICore signals are always 2-D, so "Order" admits exactly two values, and one of them is the identity. Measured against Simulink R2026a on [1 2 3; 4 5 6]:
Order = [2 1] -> [3,2] 1 4 Order = [1 2] -> [2,3], the input unchanged 2 5 3 6
The identity order is implemented rather than refused because it is a perfectly valid Simulink order, and a model that uses it has to import without being rejected - a block that does nothing is not the same as a block that cannot be represented.
This computes the same thing as Math Function's
transposeoperator, and that is fine: they are separate blocks in Simulink and separate here. Math Function reaches it through a fifteen-way operator choice; this block is named for it and takes a permutation.HDL is SYNTHESIZABLE: a permutation is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary.
Algebraic and stateless. No state space -- see the header for why.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Permute_Dimensions.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).