MinMax Running Resettable — Control Systems/Base Blocks
Control_Systems/Base_Blocks/MinMax_Running_Resettable · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
MinMax Running Resettable
Control Systems / Base Blocks
Tracks the smallest or largest value each entry of its input has taken since the last reset, chosen by the Function parameter. It is the running counterpart of the plain MinMax: that one compares what it is given now, this one remembers.
When the R port is nonzero the block forgets everything and emits the Initial Condition, and the running extreme starts again from the next sample.
Ports
- u – the signal to track, of any size [m,n]. The extreme is kept per entry, so a [m,n] input carries [m,n] independent running values.
- R – the reset, a scalar [1,1]. Any nonzero value resets, on every sample it is nonzero rather than only on the edge. It resets all entries together, not per entry.
- Output – the running extreme, the SAME size [m,n] as u.
Parameters
- Function – which extreme is tracked. This selects the comparison
rather than retuning it, so each option is a separate code path.
- Minimum (min) – the smallest so far. This is the default, as in Simulink.
- Maximum (max) – the largest so far.
- Initial Condition – a scalar seeding every entry's running value, both at the start of the run and on every reset. Defaults to 0, as Simulink's does. Note this is a genuine starting value rather than a neutral one: seeded at 0, a Maximum block never reports a negative value, because 0 is already larger than anything negative that arrives.
- Sampling Time (s) – zero or less runs the block at the model's global rate; a positive value runs it at that period. This block is discrete by nature, so it always advances one sample at a time.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries one running value per entry, and both the function and the initial condition are fixed into the generated code at export time rather than exposed as tunable parameters.
The three HDL targets are fully synthesizable. An extreme is a signed
comparison and a select, which the Q16.16 datapath does natively, so nothing has
to be evaluated in real arithmetic.
Simulink bridge
Import and export, mapped to simulink/Math Operations/MinMax Running
Resettable. "Function" to Function, one option for one option
(min, max), so that round trip is lossless; "Initial
Condition" to vinit.
The Simulink block has no SampleTime parameter, unlike
almost every other block, so the rate is not carried across: it stays on
the ICore side, and a block configured with an explicit positive rate reports
that the rate did not cross. Writing one anyway would not be a warning but a
hard error that aborts the whole generated script.
Notes
- Stateful: one running extreme per entry of the input.
- Discrete by nature – the running extreme advances one sample at a time, and there is no derivative to integrate.
- The reset discards the sample it arrives on. A reset tick emits the initial condition and the input present at that tick is not compared into anything – the running extreme restarts from the following sample. This is deliberately unlike Resettable Delay, which clears its line and then carries on with the current sample as usual.
- The reset is level-sensitive, so a reset held high for several samples resets on every one of them, not just the first.
- Deliberately carries no state space. An extreme is not linear, and resetting it on a signal makes the block time-varying as well.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/MinMax_Running_Resettable |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax_Running_Resettable |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/MinMax_Running_Resettable/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax_Running_Resettable.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/MinMax_Running_Resettable/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax_Running_Resettable.h |
| default size on canvas | 110 × 80 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | R |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Function | Minimum (min)%~%Maximum (max)~~Minimum (min) | Function |
Initial Condition | 0 | vinit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/MinMax Running Resettable |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Function | Function | Minimum (min) → min, Maximum (max) → max |
Initial Condition | vinit | passes through |
Caveat (shown to the user): the two functions map 1:1 onto Simulink's, so the choice is lossless in both directions; the Simulink block has no SampleTime parameter, so an explicit rate stays on the ICore side and is reported as not having crossed
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
MinMax Running Resettable -- the extreme of everything since the last reset THE RESET RULE WAS MEASURED, NOT ASSUMED. Verified numerically against Simulink R2026a, Function = max, initial condition -1, with R held HIGH for two consecutive samples so that a level rule and an edge rule could not give the same answer:
k : 0 1 2 3 4 5 6 7 8 9 u : 3 7 2 9 1 8 4 6 5 10 R : 0 0 0 1 0 1 1 0 0 0 y : 3 7 7 -1 1 -1 -1 6 6 10 ^^^ ^^^ ^^^ and again with Function = min, initial condition 100:
y : 3 3 2 100 1 100 100 6 5 5
Two things fall out of that, and BOTH are easy to get wrong:
- IT IS LEVEL-TRIGGERED, not edge-triggered. k = 5 and k = 6 are both high and both reset.
An edge rule would have reset only at k = 5, and the run would then agree everywhere except after a reset that stays asserted - which reads as an off-by-one somewhere else.
- ON A RESET SAMPLE THE OUTPUT IS THE INITIAL CONDITION, and the current input DOES NOT
ENTER. At k = 3 the output is -1, not max(-1, 9) = 9; u = 9 is discarded entirely, and the running extreme restarts from the NEXT sample (k = 4 gives 1, not max(9, 1)).
This is the opposite of the sibling Resettable Delay, where a reset clears the line and the tick then proceeds normally with the current sample shifted in. Carrying that block's convention over to this one produces a core that agrees on every sample except the reset ticks themselves.
So the whole behaviour is:
if (R /= 0) { running = ic ; y = ic } -- current sample discarded else { running = extreme(running, u) ; y = running }
with
runningseeded to the initial condition at the start of the run.Discrete by nature: the running extreme advances one sample at a time.
HDL is SYNTHESIZABLE here: an extreme is a signed comparison and a select, which the Q16.16 datapath does natively.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | 0 |
| 0.4 | 0.5 | 0.5 | 0 |
| 0.8 | -2 | -2 | 0 |
| 1.2 | 0.5 | 0.5 | 0 |
| 1.6 | -2 | -2 | 0 |
| 2 | 0.5 | 0.5 | 0 |
| 2.4 | -2 | -2 | 0 |
| 2.8 | 0.5 | 0.5 | 0 |
| 3.2 | -2 | -2 | 0 |
| 3.6 | 0.5 | 0.5 | 0 |
| 4 | -2 | -2 | 0 |
| 4.4 | 0.5 | 0.5 | 0 |
| 4.8 | -2 | -2 | 0 |
| 5.2 | 0.5 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__MinMax_Running_Resettable.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).