MinMax — Control Systems/Base Blocks
Control_Systems/Base_Blocks/MinMax · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
MinMax
Control Systems / Base Blocks
Outputs the smallest or the largest of what it is given, chosen by the Function parameter. The number of input ports decides which of two jobs the block does, exactly as in Simulink: with one input it reduces that signal to its extreme value, and with several it compares them entry by entry.
Ports
- Inputs – one by default, and the count is user-editable.
- With one input, of any size [m,n], the block reduces: the output is the extreme over every one of its entries.
- With several, the block works entry by entry across them. They must all be the same size [m,n], or be scalars, which are then compared against every entry of the others.
- Output – a scalar [1,1] in the reduction job; the inputs' shared size [m,n] in the elementwise one.
Parameters
- Function – which extreme is taken. This selects the comparison
rather than retuning it, so each option is a separate code path.
- Minimum (min) – the smallest. This is the default, as in Simulink.
- Maximum (max) – the largest.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Both the function and the job are fixed into the generated code at export time – the comparison is emitted directly and the loop is unrolled – so there is nothing left to retune on the generated core.
Unusually for this library, the three HDL targets are fully
synthesizable. An extreme is a signed comparison and a select, which the
Q16.16 datapath does natively, so nothing has to be evaluated in
real arithmetic and no value is converted at the port boundary.
Simulink bridge
Import and export, mapped to simulink/Math Operations/MinMax.
"Function" to Function, one option for one option
(min, max), so that round trip is lossless; the input
port count becomes Simulink's Inputs number and an imported count
becomes this port list; "Sampling Time (s)" to SampleTime, as on
every block.
CollapseMode is always written as All dimensions,
because the reduction here has no choice to offer: it collapses the whole
signal. Simulink's alternative – collapsing along one named dimension and
leaving the other – has no counterpart on this block, and an imported model
using it is reported rather than silently treated as a whole-signal
reduction.
Notes
- Algebraic, with no state: the output depends only on the current inputs.
- Not linear – an extreme is piecewise linear with a switch at the crossing, which no A/B/C/D can express – and the reduction changes the signal's shape as well, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Ties need no rule. Both functions return the same value whichever equal operand they pick, so unlike a comparison block there is no tie-breaking convention here that a backend could get wrong.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/MinMax |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/MinMax/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/MinMax/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_MinMax.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Function | Minimum (min)%~%Maximum (max)~~Minimum (min) | Function |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/MinMax |
| port-count rule | PortsParam::MinMaxCount |
SampleTime parameter | yes |
| always set | CollapseMode = All dimensions |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Function | Function | Minimum (min) → min, Maximum (max) → max |
Caveat (shown to the user): the two functions map 1:1 onto Simulink's, so the choice is lossless in both directions; the reduction collapses the whole signal, so Simulink's single-dimension CollapseMode has no counterpart here and is reported on import rather than silently treated as a whole-signal reduction
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
MinMax -- the smallest or largest of what the block is given The PORT COUNT selects between two jobs, not between one job and a wider version of it. Both are Simulink's, option for option, measured against R2026a:
ONE input REDUCTION. max over [3 -7; 2 9] -> 9, a [1,1] scalar N inputs ELEMENTWISE. max of [3 -7; 2 9] and [1 5; 8 -2] -> [3 5; 8 9]
That is why this block registers its own PortsParam kind (MinMaxCount) rather than reusing Mux's: Mux floors the exported Inputs count at TWO, and a MinMax exported as Inputs = 2 would stop being a reduction and start comparing against a port that does not exist.
Ties need no rule. min and max return the same value whichever operand they pick when the two are equal, so unlike a comparison block there is no tie-breaking convention here for a backend to get wrong. NaN is the one input where the targets could drift -- C's fmin/fmax ignore a NaN operand while a bare
<comparison propagates the other one -- so every backend here uses the plain comparison, which is what Simulink's block and ICore's own solver both do.HDL is SYNTHESIZABLE here, unusually. min and max are a signed comparison and a select, which the Q16.16 datapath does natively -- there is nothing transcendental to evaluate, so no target has to fall back to
realarithmetic.Algebraic and stateless. No state space -- see the header for why.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__MinMax.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).