Integrator — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Integrator · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Integrator
Control Systems / Base Blocks
Integrates its input with respect to time: y = ∫u dt, the transfer function 1/s. The integrator is scalar and is applied independently to every entry of the input signal, so the output has the input's size.
Ports
- Input – the signal to integrate, of any size [m,n].
- Output – the integral, of the same size.
Parameters
- Initial Value – the state at the start of the run. A scalar is used for every entry.
- Limit Output – off or on. When on, the output is held inside the saturation band and integration stops at a limit instead of winding up.
- Upper Saturation Limit / Lower Saturation Limit – the band, used only while limiting is on. They default to the widest finite doubles, which stand in for Simulink's ±infinity.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The exported block carries the discretization of the scalar 1/s system for the run's method, so generated code matches the in-app simulation for every method, not just forward Euler.
Simulink bridge
Import and export, mapped to simulink/Continuous/Integrator.
"Initial Value" to InitialCondition, "Limit Output" to
LimitOutput, "Upper/Lower Saturation Limit" to
UpperSaturationLimit/LowerSaturationLimit, and
"Sampling Time (s)" to SampleTime.
External reset does not cross: it shows a second input port in Simulink,
and no config value here can add or remove a port. An imported Integrator using
it is reported rather than silently mistranslated.
Notes
- Stateful: one continuous state per input entry.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Integrator |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Integrator |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Integrator/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Integrator.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Integrator/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Integrator.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Value | 0 | InitialCondition |
Limit Output | off%~%on~~off | LimitOutput |
Upper Saturation Limit | 1e+308 | UpperSaturationLimit |
Lower Saturation Limit | -1e+308 | LowerSaturationLimit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Continuous/Integrator |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Value | InitialCondition | passes through |
Limit Output | LimitOutput | off → off, on → on |
Upper Saturation Limit | UpperSaturationLimit | passes through |
Lower Saturation Limit | LowerSaturationLimit | passes through |
Caveat (shown to the user): external reset is not supported; output limiting is
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Integrator block — per-entry scalar integrator A unit integrator 1/s (continuous SS: A=0, B=1, C=1, D=0) applied INDEPENDENTLY to every entry of the input port signal. The output port carries the SAME signal size as the input, and each entry owns its own scalar state. "Initial Value" is the (per-entry) initial state.
Simulation: the in-app discrete sim runs the scalar recursion per entry on the discretized unit integrator: y[k] = c*x[k] + d*u[k] (output from the CURRENT state) x[k+1] = a*x[k] + b*u[k] (state update) where (a,b,c,d) = (Ad, Bd, Cd, Dd) of the 1x1 unit integrator discretized per the block's method. The continuous sim is just dx/dt = u, y = x.
Code export (Python/MATLAB/Java/Rust/C/C++ and HDL/PLC) Every generator realizes the SAME scalar recursion per [r,c] entry, structurally identical to the in-app simulation, with (a,b,c,d) embedded as constants and the per-entry state seeded with the (embedded) Initial Value. integratorDiscreteScalars() calls discretize() then reads the discrete SS — so, unlike forward-Euler-only hard-coding, the export matches the in-app sim for EVERY discretization method (ZOH/FOH/Impulse/Tustin/Matched/Forward&Backward Euler).
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 16.82 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0.9965 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.45 … 1.9 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Integrator.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).