In Bus Element — Control Systems/Base Blocks
Control_Systems/Base_Blocks/In_Bus_Element · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
In Bus Element
Control Systems / Base Blocks
Takes a stacked signal apart, selecting a run of its elements:
y = u(k … k+n−1, :), where k is Element Index and n is Number of Elements.
It is the inverse of Mux: where Mux stacks several signals into one column, this pulls one of them back out.
Ports
- Input – the stacked signal, any size [m,n]. Selection is by ROW, so a Mux of three scalars is three selectable elements.
- Output – the selected rows, size [Number of Elements, n] – the same column count as the input. Selecting one element from a stacked column therefore gives a scalar.
Parameters
- Element Index – which element the selection starts at, counting from 1. It must be a whole number of at least 1, and the selection must fit inside the input: index + count − 1 may not exceed the input's row count.
- Number of Elements – how many consecutive rows to take. A whole number of at least 1; the default of 1 selects a single element.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The selection is resolved at export time, so nothing is exposed as a tunable parameter and the emitted body is a fixed set of element copies with no arithmetic. That also makes the three HDL targets genuinely synthesizable rather than simulation-only: selecting a wire is free in hardware.
Simulink bridge
No Simulink equivalent, and the reason is structural rather than a gap. Simulink's In Bus Element is two things at once: an inport, which is a subsystem's boundary object, and a selector that picks one element out of the bus arriving there. ICore's boundary object is the Subsystem Input Gate, which is created by the subsystem that owns it and is not a library block at all; and ICore has no bus type, a bundle of signals being a stacked column. This block is therefore the SELECTOR half only, and there is no single Simulink block that is the same thing. The bridge reports it rather than guessing a mapping.
Moving a model by hand: a Simulink In Bus Element becomes an ICore subsystem input gate carrying the whole stacked signal, plus one of these blocks per element read from it.
Notes
- Algebraic and stateless: the output is a copy of part of the input at the same instant.
- Selection is by ROW and keeps every column, so a matrix input gives a matrix output of the same width. Pair it with Reshape or Squeeze if a different shape is wanted.
- An out-of-range selection stops the run and names the block, rather than reading past the end of the signal.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/In_Bus_Element |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_In_Bus_Element |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/In_Bus_Element/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_In_Bus_Element.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/In_Bus_Element/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_In_Bus_Element.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Element Index | 1 | — |
Number of Elements | 1 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's In Bus Element is an INPORT that also selects a bus element, and the two halves cannot both be an ICore library block. ICore's inport is the Subsystem Input Gate (Blocks/Private/), created by the subsystem that owns it rather than dragged in from the navigator, and ICore has no bus type -- a bundle of signals is a stacked column. This block is the SELECTOR half, the inverse of Mux, and no single Simulink block is the same thing. Moving a model by hand: a Simulink In Bus Element becomes a subsystem input gate carrying the whole stacked signal plus one of these per element read from it.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
In Bus Element block — selects one element, or a run of them, out of a stacked signal y = u(k .. k+n-1, :) -- the rows starting at "Element Index", "Number of Elements" of them.
WHY THIS BLOCK HAS AN INPUT, WHEN SIMULINK'S HAS NONE. Simulink's In Bus Element is two things at once: it is an INPORT -- a subsystem's boundary object -- and it SELECTS one element out of the bus arriving there. ICore's boundary object is the Subsystem Input Gate, which lives in Blocks/Private/ and is deliberately not a library block: a gate is created by the subsystem that owns it, not dragged in from the navigator. And ICore has no bus type -- a bundle of signals is a stacked column, which is what Mux builds.
So the two halves cannot both be here, and this block is the half that ICore was missing: the SELECTOR. It is the inverse of Mux -- Mux stacks several signals into one column, this takes a column apart again -- and it lives beside Mux in Base_Blocks for that reason rather than in Sources, which is where Simulink files its inport. A block with an input port would read as a mistake in a family whose every other member generates a signal from nothing.
It registers Support::None with that reasoning, so the bridge REPORTS it rather than silently dropping it or asserting a mapping that does not hold.
Code export: all ten targets, all genuinely synthesizable on the three HDL ones -- the selection is decided at export time, so the emitted code is a fixed set of element copies with no arithmetic, no clock and no state.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__In_Bus_Element.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).