Find NonZero Elements — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Find_NonZero_Elements · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Find NonZero Elements
Control Systems / Base Blocks
Reports which entries of its input are not zero, rather than their values: it scans the signal and outputs the linear indices of every entry with u ≠ 0, in ascending order, together with how many it found. Entries are scanned down each column and then across, which is how MATLAB and Simulink number the elements of an array.
Ports
- u – the signal to scan, of any size [m,n]. The test is an exact comparison against zero, not a threshold.
- idx – the indices found, as a column of fixed height m×n. The first N entries are the indices, ascending; every entry after them is 0, which is padding rather than a result. Read it together with N.
- N – a scalar [1,1]: how many nonzero entries were found, and so how many entries of idx are meaningful. It is 0 when the whole input is zero, and m×n when none of it is.
Parameters
- Index Mode – whether the reported indices are One-based (the first element is 1, the default and MATLAB's convention) or Zero-based (the first element is 0, C's convention). It shifts the numbers written into idx and nothing else; the padding stays 0 in both, which is why N is not optional in Zero-based mode.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core: the index mode shifts constants that are resolved at export time.
Every target emits the same scan – a counter, then one test per input entry, each writing a constant index at a position the data decides – so the emitted code grows with the element count rather than with its square. The three HDL targets are fully synthesizable and hold the counter in the fixed-point base's integer scratch; Structured Text keeps the list in a local array because its output tokens are resolved to fixed positions.
On the HDL targets the comparison is against a QUANTIZED zero. An HDL port carries Q16.16, whose quantum is about 1.5×10-5, so an entry smaller than that arrives as exactly zero and is reported as a zero the reference counted as nonzero. This is inherent to the datapath, not to the code: the information is lost at the port. Drive the block with values that are either zero or comfortably clear of it.
Simulink bridge
Neither direction. Simulink's counterpart (simulink/Math Operations/Find Nonzero Elements) emits a variable-size signal whose length is the number of elements it found on that step. ICore sizes every port once when the model is built, so the same answer has to be carried as a fixed column plus a count – two output ports where Simulink has one, and a different signal on the one they share. A model exchanged through that pairing would not be the same model, so the bridge reports the block rather than translating it. Simulink's optional nonzero input values output has no counterpart for the same reason a config here can never add or remove a port.
Notes
- Algebraic, with no state: the output depends only on the current input.
- No state space, and not because the block is nonlinear in the usual way: it reports positions, and no A/B/C/D produces an index. Model reduction reports it as unmergeable.
- The zero test is exact. A value that is merely small is nonzero, and −0 compares equal to zero, so it is not reported. Put a Dead Zone or a Quantizer in front if you need a tolerance.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Find_NonZero_Elements |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Find_NonZero_Elements |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Find_NonZero_Elements/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Find_NonZero_Elements.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Find_NonZero_Elements/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Find_NonZero_Elements.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | idx |
| 3 | out | ICoreDouble | N |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Index Mode | One-based%~%Zero-based~~One-based | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Find Nonzero Elements emits a VARIABLE-SIZE signal whose length is the number of elements found on that step; an ICore port is sized once when the model is built, so the same answer is carried here as a fixed zero-padded index column PLUS a count -- two output ports against Simulink's one, and a different signal on the port they share. The two cannot be exchanged without changing the model, so the block is reported rather than translated.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Find NonZero Elements block -- report which entries of a signal are not zero Two outputs: a column of the LINEAR indices of the nonzero entries, ascending, and how many there were. Entries are scanned down each column and then across -- MATLAB's linear order -- so index 2 of a [3,2] signal is the second entry of the FIRST column. Algebraic, stateless, and no state space (an index is not a linear function of the values; see the header).
The index column is a FIXED [m*n, 1] and is zero-padded past the count. That is not a simplification of Simulink's variable-size output, it is the only shape ICore can carry: a port is sized once at model build, and a port whose width changed between steps produces a ragged run. The count output is what keeps the padding readable -- in Zero-based mode 0 is a real index, so the pad value alone cannot say where the list stops.
Every backend runs the SAME scan: a counter starting at zero, one conditional per input entry, each writing a COMPILE-TIME constant index at a run-time position. Only the position is data-dependent, which is what keeps the emitted code linear in the element count rather than quadratic, in all ten languages.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 | out ICoreDouble-Out-1 |
|---|---|---|---|
| 0 | -2 | 1 | 1 |
| 0.4 | 0.5 | 1 | 1 |
| 0.8 | -2 | 1 | 1 |
| 1.2 | 0.5 | 1 | 1 |
| 1.6 | -2 | 1 | 1 |
| 2 | 0.5 | 1 | 1 |
| 2.4 | -2 | 1 | 1 |
| 2.8 | 0.5 | 1 | 1 |
| 3.2 | -2 | 1 | 1 |
| 3.6 | 0.5 | 1 | 1 |
| 4 | -2 | 1 | 1 |
| 4.4 | 0.5 | 1 | 1 |
| 4.8 | -2 | 1 | 1 |
| 5.2 | 0.5 | 1 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Base_Blocks__Find_NonZero_Elements.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).