Complex To Real Imag — Control Systems/Base Blocks
Control_Systems/Base_Blocks/Complex_To_Real_Imag · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Complex to Real-Imag
Control Systems / Base Blocks
Takes a complex signal apart into its real and imaginary parts, entry by entry: re = real(u), im = imag(u). It is how a complex value reaches a block that reads real ones – a Scope, a Gain, an export boundary.
Ports
- Input – the signal u, of any size [m,n]: a complex one (type
ICoreComplex, badge
cplx), or a real one, whose imaginary part is zero. - Re – the real part, of size [m,n]. With Output set to Imag this one port is the imaginary part instead.
- Im – the imaginary part, of size [m,n], present only with Output set to Real and imag. With Real or Imag the block has ONE output. The ports are added and removed by hand: the run stops, naming the block, when their count does not match Output.
Parameters
- Output – Real and imag (both parts, the default), Real or Imag.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. A complex signal is stored as its two parts side by
side in the target's own numbers – element k's real part, then its
imaginary part, the layout of Simulink Coder's creal_T arrays
– so the block is a copy out of that layout and does no arithmetic. The
three HDL targets are therefore fully synthesizable; each part is
a Q16.16 value there, as every signal is.
Simulink bridge
Import and export, mapped to simulink/Math Operations/Complex to
Real-Imag. "Output" ↔ Output (the same three choices) and
"Sampling Time (s)" ↔ SampleTime. Setting Output
moves Simulink's ports, and an imported block takes the port count it
implies.
Notes
- Algebraic, with no state: the output depends only on the current input.
- No state space: its input may be complex, and model reduction is real.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Base_Blocks/Complex_To_Real_Imag |
| family | Control_Systems/Base_Blocks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Complex_To_Real_Imag |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Complex_To_Real_Imag/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Complex_To_Real_Imag.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Base_Blocks/Complex_To_Real_Imag/ICoreBlock_0_Control_Systems_1_Base_Blocks_2_Complex_To_Real_Imag.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreSignalType::COMPLEX_ID | — |
| 2 | out | ICoreDouble | Re |
| 3 | out | ICoreDouble | Im |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output | Real and imag%~%Real%~%Imag~~Real and imag | Output |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Math Operations/Complex to Real-Imag |
| port-count rule | PortsParam::RealImagOutputs |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Output | Output | Real and imag → Real and imag, Real → Real, Imag → Imag |
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Complex to Real-Imag block -- a complex signal's real and imaginary parts re = real(u), im = imag(u), entry by entry. Simulink's ComplexToRealImag: Output chooses which parts are outputs -- both, or one of them. A REAL input is taken too, as R2026a takes one (measured: [1 2] gives re [1 2] and im [0 0]).
The input is an ICoreComplex port (FEATURES_TO_ADD.md BF23.1). A complex value arrives as an r x 2c matrix for an [r, c] signal -- column 2k is element k's real part, 2k+1 its imaginary part -- and a real one as the r x c it is; which of the two arrived is the SOURCE's kind, read at the build and at the export alike. Every target therefore reads the doubles it already stores, and this block is a strided copy in all ten of them, so the three HDL targets are fully synthesizable.
The output list follows Output, as Simulink's does: two ports for "Real and imag", one for the others. The ports are edited by hand, as Receive's status is, and the build checks the count against the choice.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.